The general principle of such a converter is as follows: a sample-and-hold module supplies a stabilized analogue voltage for a brief period of time which is the time necessary for conversion. A set of comparators in parallel compares this voltage to reference voltages defined by a series resistor network supplied by a constant current.
Comparator structures having differential inputs are preferably used because they eliminate the errors arising from common mode voltage fluctuations. In this case, the following structure is generally used: the voltage to be converted, in the form of a differential voltage Vin−VinN is applied to the input of the sample-and-hold module S/H which has a differential structure; the complementary differential outputs VS and VSN of the sample-and-hold module, representing the voltage to be converted (VS−VSN is equal to Vi−VinN) are applied to two networks of N precision resistors in series; the current I0 in the networks is fixed by the identical current sources; the intermediate terminals between the resistors of the two networks are applied in pairs to the inputs of the N comparators in the following manner: the row i resistor of the first network (supplied by VS) and the N-i row resistor of the second network (supplied by the complementary voltage VSN) are connected to the inputs of the row i comparator COMPi. The comparators switch in one direction or another depending on the level of the differential voltage VS−VSN, and it may be stated in summary that if the voltage VS−VSN corresponds to the switching threshold of the row i comparator, all the comparators of a row less than i will switch in one direction and all the comparators of a row greater than i will switch in the other direction; the state of the comparator outputs therefore provides a digital indication of the level of the input differential analogue voltage.
This arrangement is shown in FIG. 1.
For fast comparators, intended to provide a digital signal at a high sampling frequency and capable of receiving an analogue input voltage which may vary rapidly, the problem then arises of the response time constant of the structure which has just been described: the resistor network comprises numerous resistors since a high resolution is desired for the comparator. These resistors themselves have a parasitic capacitance and they are connected to comparators which also have parasitic capacitances. The combination of these resistors and of these parasitic capacitances results in transmission time constants between the outputs of the sample-and-hold module and the inputs of the comparators.
These time constants in particular have the following detrimental effect: since the resistor networks are crossed, the row i comparator receives on one input a voltage VS-i.r.I0 after a delay which is broadly related to the time constant introduced by a set of i unit resistors with value r in series, while it receives on another input the voltage VSN−(N-i).r.I0 after a delay which is related instead to the time constant introduced by a set of N-i resistors. It will therefore be understood that this causes no particular problem when i and N-i are nearly identical, but that it does cause a problem when i is close to zero or to N and N-i is close to N or zero: in these cases the time constants are in fact very different, which means that the comparator in question will receive one voltage level more rapidly on one input than on the other. Over this time interval it may quite simply provide a false indication. There is therefore a risk that those comparators which are on the borderline between switching in one direction or in the other will provide an incorrect indication. The higher the resolution or the conversion frequency, the greater the susceptibility to this error.